P84: PRESAGE: Selective Low Overhead Error Amplification
for Easy Detection
SessionPoster Reception
Event Type
ACM Student Research Competition
Poster
Reception
TimeTuesday, November 14th5:15pm -
7pm
LocationFour Seasons Ballroom
DescriptionSoft-errors remain a vexing challenge. Today's error
detectors either come with high false positives or high
omissions. Our work focuses on not losing an error sown,
but amplifying it so that cheap detection is enabled.
Consider structured address generation in loops where data from a base address plus offset is used. An erroneous offset no longer crashes today's applications thanks to large address spaces; instead, it silently corrupts data (unintended fetch). We relativize address generation using LLVM, thus each new address is not base plus offset but previous relative address plus offset. If one address is corrupted, all future address are corrupted in a chain. This permits efficient loop exit-point detection.
Relativization has low overhead, actually lowered by some ISAs down to zero. These advantages survive crucial compiler memory access
optimizations. We demonstrate 100% SDC detection for a class of benchmarks with respect to structured address protection.
Consider structured address generation in loops where data from a base address plus offset is used. An erroneous offset no longer crashes today's applications thanks to large address spaces; instead, it silently corrupts data (unintended fetch). We relativize address generation using LLVM, thus each new address is not base plus offset but previous relative address plus offset. If one address is corrupted, all future address are corrupted in a chain. This permits efficient loop exit-point detection.
Relativization has low overhead, actually lowered by some ISAs down to zero. These advantages survive crucial compiler memory access
optimizations. We demonstrate 100% SDC detection for a class of benchmarks with respect to structured address protection.
