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P78: Performance Evaluation of Graph500 Considering CPU-DRAM Power Shifting


Authors: Yuta Kakibuka (Kyushu University), Yuichiro Yasui (Kyushu University), Takatsugu Ono (Kyushu University), Katsuki Fujisawa (Kyushu University), Koji Inoue (Kyushu University)

Abstract: There are power constraints on computer systems which comes from technical, costly or social demands. Power wall is one of the most serious issues for post petascale high-performance computing. A promising solution to tackle this problem is to effectively manage power resources based on the characteristics of workloads. In power constrained computing, the key is to translate the limited power budget into sustained performance effectively. To achieve this goal, assigning the appropriate amount of power budget to each hardware component, or power shifting, is a critical challenge.

In this work, we focus on large-scale graph processing. Graph analysis algorithms are increasing its importance with growing demands of big data analysis. However, the impact of power constraint on the performance of graph processing application is not declared. Our work is the performance evaluation of Graph500 under power constraints to CPU and DRAM.

Award: Best Poster Finalist (BP): no

Poster: pdf
Two-page extended abstract: pdf


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