DescriptionTaking an inspiration from Software Defined Networking and Network Functions Virtualization, also the HPC world has the opportunity to switch to much more flexible network programming paradigm. The P4 language was originally designed for a description of networking switches’ dataplane. However, we examine using it in a related domain: SmartNICs. We see the P4 as an interface for application designers to formally express their requirements for the functionality of the network. This achievement can be further extended by embedding hardware accelerators (such as modules for pattern matching, cryptography, etc.) into the FPGA based SmartNIC. Network-related parts of the compute load can be then moved into the networking hardware, effectively blurring the edge between the HPC network and compute components.
The work of FPGA firmware developers is by no means replaced by the P4 to FPGA compiler. Rather, firmware developers can spend less time over small changes and other mundane tasks and will be able to focus on more complex tasks, such as effective architectures and algorithms for network-compute accelerators. In order to demonstrate the feasibility of P4 for high-speed packet processing in FPGA, we use two existing and mature FPGA-based projects: Netcope Packet Capture is an FPGA firmware capable of 100 Gbps line rate traffic filtering and forwarding to output network ports or host RAM via PCI Express.