P52: A Simulation-Based Analysis on the Configuration of Burst Buffer
Abstract: Burst buffers have been widely deployed in many supercomputer systems to absorb bursty I/O and accelerate I/O performance. Previous work has shown that with burst buffer systems, I/O operations from computer nodes can be greatly accelerated. Different configurations of burst buffers can have huge impact on performance of applications. However, the proper configuration of burst buffers for given systems and workloads still remains an open problem. In this paper, we address this challenge by simulating the behavior of a burst buffer under different buffer sizes with trace logs from a set of HPC applications in a distributed environment. We tuned our simulator with a production level burst buffer system. From the results of the simulation, we found that for most of HPC applications, using a buffer size that is less than half of the total access space of the application can still achieve high performance.
Award: Best Poster Finalist (BP): yes
Two-page extended abstract: pdf