Reconfigurable Computing in Exascale
Authors: Dr. Sven Karlsson (Technical University of Denmark)
Abstract: While traditional HPC systems continue making great advances, it is argued that paradigm shifts, including radical new architectures, are needed to continue scaling performance beyond exascale at sustainable cost and energy levels. Such architectures will likely employ reconfigurability or FPGAs for certain types of parallelism.
This BoF targets persons interested in these subjects aiming to further understand their role, usage, run-time systems, programming models, the role of open-source technology and what challenges to widespread adoption remain. One goal is also to continue to build a HPC FPGA community.
The BoF will combine interactive presentations with audience driven discussions.
Long Description: Despite the emergence of the first 100PF systems, sustainable and
affordable Exascale computing remains a grand challenge. Systems need
to scale across a range of diverse applications. Significant energy
efficiency improvements are needed. Application developers must find
it easy to target the systems. For future systems to meet the needs,
it is argued that a paradigm shift, including radical new
architectures, will be necessary for high performance computing to
reach beyond Exascale performance.
Such architectures will likely employ different levels of parallelism
ranging all the way from coarse grain, on high performance CPU cores,
via GPGPUs, to fine-grain on accelerators and FPGAs.
The FPGA landscape is changing quickly. The ever increasing cost of
ASIC development and fabrication forces developers of even high
end systems to consider FPGAs for implementation. This has in turn
opened up the market for ever more powerful FPGA devices. We now see
devices with advanced and powerful floating point units, high end
serial transceivers and support for fast die-stacked memory.
Another, complementary, line of development is tighter integration of
FPGA fabrics and traditional CPUs as well as ASICs. All major FPGA
vendors now offer high performance CPU cores integrated with FPGA
fabrics. Similarly, Intel has announced its intent to build CPU/FPGA
multi-chip modules with coherent memory access. Another interesting
example is Achronix which recently announced a FPGA fabric IP block
for inclusion into ASICs.
All these technologies are relevant to the HPC community. It becomes
increasingly difficult to ignore the opportunity of leveraging
powerful FPGA devices to enable continued performance scaling.
The community has often discussed the usage of FPGAs in Exascale
systems. However, as of yet there is no clear consensus as to what
precise role FPGAs are to play as programmability, while improving,
remains a challenge.
The purpose of the BoF session is to further understand the role of
FPGAs and to accelerate their acceptance. This will be done through a
series of short positional talks which will draw the audience into the
discussion. Attendees will get floor time to present their views as
well. We plan to end the BoF with an informal panel where the audience
can interact with the speakers and address longer term questions.
The currently confirmed list of speakers are:
* Glen Edwards, Micron
* Tobias Becker, Maxeler
* Mondrian Nuessle, University of Heidelberg and Extoll
* Niko Neufeld, CERN
* Michael Strickland, Intel
* Jordà Polo, Barcelona Supercomputing Center
* Dan Ernst, Cray
* Happy Sithole, Center for High Performance Computing in South Africa
The BoF will produce a report summarizing and concluding the
viewpoints of speakers and the audience. Its most important expected
result will be the creation of a community of practice for persons
interested in the use of FPGAs in HPC.
With its focus on forging a community, this is a new BoF not held
before. It builds on and combines the activities started at SC16 and
ISC 2017 by some of the organizers.
Conference Presentation: pdf
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