Usability, Scalability and Productivity on Many-Core Processors: Intel Xeon Phi

Authors: Dr. Hai Ah Nam (Los Alamos National Laboratory)

BP
Abstract: Recent deployments of large-scale Intel Xeon Phi processor (Knight Landing)-based systems have provided users with early experiences on many-core processors. This BoF, conducted by the Intel Xeon Phi Users Group (IXPUG), will provide a forum for application and tool developers, HPC center staff, and industry experts to discuss their successes and challenges. This BoF will showcase code optimization successes, particularly, how to achieve usability, scalability and productivity on KNL-based systems through invited talks, a panel session and a community Q&A. IXPUG is an independent users group for anyone interested in application performance on the Intel Xeon Phi. See http://ixpug.org

Long Description: Many-core architectures are paving the way toward future exascale systems. However, achieving the desired performance requires code modernization to exploit new architectural features, such as AVX512 and high-bandwidth MCDRAM memory. The recent deployments of large-scale 2nd generation Intel Xeon Phi, Knights Landing (KNL), HPC platforms have provided users with early experiences on this new many-core processor, and in particular, how to achieve usability, scalability and productivity on KNL-based systems.

This BOF, conducted by the Intel Xeon Phi Users Group (IXPUG), will provide a forum for application and tool developers, HPC center staff, and industry experts to discuss their successes and challenges. This BOF is about sharing ideas, implementations, and experiences that will help users take advantage of new Intel Xeon Phi features on large-scale KNL-based systems.

BOF attendees will experience an open forum with fellow application programmers, software developers, Intel Xeon Phi architecture designers, and compiler and tool experts. Application performance and scalability challenges at all levels will be covered, focusing on application tuning on large HPC systems with many KNL devices. The BOF will showcase code optimization successes through invited talks, a panel session and a community Q&A.

This BOF is the next in a line of highly successful community engagements that include BOFs the last three years at SC and ISC, annual IXPUG meetings and workshops hosted by member sites located in the United States, Europe, and Russia and online working groups. IXPUG events often fill or overflow their venues, with attendance of about 150 at past SC BOFs. Events foster sharing of community best practices, presentations on newly developed tools and methodologies, and setting research agendas for improving performance across a wide range of application domains. Researchers are finding that others have experiences, innovations, tips and methodologies to share that they find useful in their own work – from moderately sized clusters up to the world’s largest Xeon Phi system installations.

Presentations and a summary of the BOF will be made publicly available on the IXPUG web site (http://ixpug.org).

Expected Outcomes: • Users of the Intel Xeon Phi Knights Landing HPC platforms will be able to share and learn about the current research on efficient use of KNL-based systems • Identify best practices for using many-core systems • Identify challenges facing the applications development community to inform the vendor community on needed support, tools and future architecture designs • Understanding how to use the KNL will increase adoption of future many-core architectures on the path to exascale computing

Conference Presentation: pdf

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